ARM AMBA NIC-301 Especificações descarregar pdf (Página 88)

Programmers Model

ID062813 Non-Confidential

Figure 3-16 Test chip CFGREG12 Register bit assignments

Table 3-18 shows the bit assignments.

Test chip SCC Registers 13, 15, 17, 19, 23, and 25 PLL control registers

The CFGREG10, CFGREG13, CFGREG15, CFGREG17, CFGREG19,

CFGREG21,CFGREG23, and CFGREG25 Register characteristics are:

Purpose CFGREG13, CFGREG15, CFGREG17, CFGREG19, CFGREG21,

CFGREG23, and CFGREG25 PLL are PLL control registers.

Together with the CFGREG14, CFGREG16, CFGREG18, CFGREG20,

CFGREG22, CFGREG24, and CFGREG26 PLL value registers, they

enable you to read and write PLL configuration settings as follows:

• CFGREG13 and CFGREG14 control SYS PLL.

• CFGREG15 and CFGREG16 control DDR PLL.

• CFGREG17 and CFGREG18 control HDLCD PLL.

• CFGREG19 and CFGREG20 control A15 PLL 0.

• CFGREG21 and CFGREG22 control A15 PLL 1.

• CFGREG23 and CFGREG24 control A7 PLL 0.

• CFGREG25 and CFGREG26 control A7 PLL 1.

See Clocks on page 2-24.

Usage constraints Bit 5 is read-only.

Configurations Not applicable.

Attributes See Table 3-6 on page 3-13.

31 0

0 00000 0 0000000000000 0000 000000 00

Reserved

A15_CRNTCLK[3:0]

A7_CRNTCLK[3:0]

Table 3-18 Test chip CFGREG12 Register bit assignments

Bits Name Function

[31:8] - Reserved. Do not modify.

[7:4] A15_CRNTCLK[3:0] Indicates the source for the A15_ CLK:

b0001

Source is CPU_CLK0_A15.

b0010

Source is CPU_CLK1_A15.

b0100

Source is SYSCLK.

b1000

Source is CPU_CLK0_A15/2.

See Figure 2-10 on page 2-26.

[3:0] A7_CRNTCLK[3:0] Indicates source for A7_ CLK: