ARM AMBA NIC-301 Especificações descarregar pdf (Página 53)

Hardware Description

ID062813 Non-Confidential

2.9 HDLCD

An ARM HDLCD controller in the Cortex-A15_A7 MPCore test chip provides graphic display

capabilities. The controller is a frame buffer device that is capable of displaying up to

1920×1080p pixel resolution at 60Hz with a 165MHz pixel clock from OSCCLK 5. The MMB

connects the 24-bit RGB data directly between the test chip and the motherboard through the

HDRY header. The multiplexer FPGA on the motherboard can select this bus to drive the analog

and digital interfaces for the DVI connector using the motherboard SYS_CFG register interface.

See the Motherboard Express µATX Technical Reference Manual.

The HDLCD frame buffer is located in DDR2 memory serviced by the DMC from the test chip

bus matrix. This ensures maximum data bandwidth between the Cortex-A15_A7 MPCore

cluster, the HDLCD controller, and DDR2 memory without accessing off-chip devices.

Figure 2-14 shows a functional overview of the HDLCD controller and its connections to the

Cortex-A15 test chip and the motherboard.

See Appendix B HDLCD controller for a full description of the HDLCD controller.

Figure 2-14 HDLCD graphics system interconnect

CoreTile Express A15x2 A7x3

Daughterboard

LogicTile Express

FPGA Daughterboard

Motherboard Express μATX

V2M-P1

HDRY HDRY

HDRY2HDRY1

Cortex-A15_A7

Test Chip

HDLCD

NIC-301 AXI interconnect

DMC

24-bit RGB data,

synch and clock

OSCLK 5

DDR2

MMB1 MMB2

Multiplexer FPGA

MMB1 MMB2

FPGA

IOFPGA

RGB to DVI

analog

RGB to DVI

digital

DVI

Cortex-A15

MPCore Cluster

+NEON

Cortex-A7

MPCore Cluster

+NEON

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