ARM AMBA NIC-301 Especificações descarregar pdf (Página 81)

Programmers Model

ID062813 Non-Confidential

[15:13] A7_NCPURESET[2:0] This reset operates independently of nRESET:

Reset.

Non-reset.

The default is

b111

See Table 2-1 on page 2-15, Internal resets on page 2-17, and the Cortex

-A7 MPCore

™

Technical Reference Manual

Note

The Cortex

-A7 MPCore

™

Technical Reference Manual names this signal as

nCOREPORESET.

[12] Reserved Reserved. Do not modify.

[11] A15_NVSOCRESET

Reset.

Non-reset.

The default is

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A15 Technical Reference Manual.

[10] A15_NVCORERESET

Reset.

Non-reset.

The default is

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A15 Technical Reference Manual.

[9] A15_NPRESETDBG This reset operates independently of nRESET:

Reset.

Non-reset.

The default is

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A15 Technical Reference Manual.

[8] A15_NL2RESET This reset operates independently of nRESET:

Reset.

Non-reset.

The default is

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A15 Technical Reference Manual.

[7:6] A15_NDBGRESET[1:0] This reset operates independently of nRESET:

Reset.

Non-reset.

The default is

b11

. See Table 2-1 on page 2-15, Internal resets on page 2-17, and the

Cortex

-A15 Technical Reference Manual.

Table 3-13 Test chip CFGREG6 Register bit assignments (continued)

Bits Name Function

1 2 ... 76 77 78 79 80 81 82 83 84 85 86 ... 177 178

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