ARM AMBA NIC-301 Especificações descarregar pdf (Página 112)

Programmers Model

ID062813 Non-Confidential

Note

The default level-2 data and tag RAM latency values in the level-2 control register in the

Cortex-A15 cluster are set to 2 cycles. You must increase these values to 3 cycles to match the

high-density RAMs used for the level-2 memory. You must perform this initialization in your

OS boot code. See the Cortex

-A15 Technical Reference Manual for more information on the

Cortex-A15 cluster Level-2 control register.

3.4.3 Cortex-A7 cluster

The Cortex-A15 cluster, version r2p1, consists of three Cortex-A7 cores with NEON media

processing technology, SIMD extension, and FPU. The L1 memory subsystem has 32KB of

instruction cache and 32KB of data cache for each core.

For information about the programmable devices within the Cortex-A7 cluster, see the

Cortex

-A7 MPCore

™

Technical Reference Manual.

3.4.4 Cortex-A7 L2 cache controller

Table 3-33 provides information on the Cortex-A7 Level-2 cache controller implementation.

Default data and tag RAM latencies 2 cycles.

Release version Not applicable.

Reference documentation Cortex-A15 Technical Reference Manual.

Table 3-32 Cortex-A15 Level-2 cache controller implementation (continued)

Property Value

Table 3-33 Cortex-A7 Level-2 cache controller implementation

Property Value

Memory base address Not applicable. The L2-cache controller is integrated into the Cortex-A7 cluster.

Cache size 512KB.

Number of ways 8.

Line size 64 bytes.

Master port Single 128-bit ACE interface.

Slave port No ACP interface.

Physically indexed and tagged cache -

Default data RAM latency 2 cycles.

Release version Not applicable.

Reference documentation

Cortex

-A7 MPCore

™

Technical Reference Manual.

1 2 ... 107 108 109 110 111 112 113 114 115 116 117 ... 177 178

Sem comentários

ARM AMBA NIC-301 Especificações Página 112