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Programmers Model

ID062813 Non-Confidential

Note

The default level-2 data RAM latency value in the level-2 control register in the Cortex-A7

cluster is set to 2 cycles. This is sufficient for the Cortex-A15_A7 test chip to function correctly

and you do not need to alter this value. See the Cortex

-A7 MPCore

™

Technical Reference

Manual for more information on the Cortex-A7 cluster Level-2 control register.

3.4.5 GIC-400 Interrupt controller

The Cortex-A15 and Cortex-A7 clusters do not contain internal controllers. The

Cortex-A15_A7 test chip contains a GIC-400 interrupt controller that both the Cortex-A15 and

Cortex-A7 clusters share. The cluster signals connect to interfaces on the GIC-400 controller:

• Cortex-A15 signals connect to GIC-400 core interfaces 0 and 1.

• Cortex-A7 signals connect to GIC-400 interfaces 2, 3, and 4.

Table 3-34 shows information on the implementation of the GIC-400.

Table 3-34 Interrupt controller implementation

Interrupt controller block Property Value

GIC-400 Memory base address

0x00_2C00_0000

Reserved Offset from base address

0x00_0000_0000

0x00_0000_0FFF

Interrupt controller distributor Offset from base address

0x00_0000_1000

0x00_0000_1FFF

Interrupt controller physical core interface Offset from base address

0x00_0000_2000

0x00_0000_3FFF

Interrupt controller virtual core interface, hypervisor view

for requesting core

Offset from base address

0x00_0000_4000

0x00_0000_4FFF

Interrupt controller virtual core interface, hypervisor view

for all cores

Offset from base address

0x00_0000_5000

0x00_0000_5FFF

Interrupt controller virtual core interface, virtual machine

view

Offset from base address

0x00_0000_6000

0x00_0000_7FFF

- Release version ARM GIC-400 r0p0

- Reference Documentation

CoreLink

™

GIC-400 Generic Interrupt

Controller Technical Reference Manual

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