ARM AMBA NIC-301 Especificações descarregar pdf (Página 18)

Hardware Description

ID062813 Non-Confidential

Clock generators

The daughterboard provides nine on-board OSCCLKS to drive the core and

internal AXI, AXIM, DDR2, SMC, and HDLCD interfaces.

CoreSight software debug (P-JTAG) and trace ports

The Cortex-A15_A7 MPCore test chip CoreSight system supports both the SWD

and P_JTAG protocols.

A 32-bit trace interface is provided through the standard dual 16-bit Matched

Impedance ConnecTOR (MICTOR) connectors.

System interconnect

HDRX header Connects the multiplexed AXI master bus, HSB M, to the

external AXI slave on the other daughterboard in Site 2 of

the V2M-P1 Motherboard Express.

HDRY header Connects the Configuration Bus (CB), the System Bus (SB),

the Static Memory Bus (SMB) and the MultiMedia Bus

(MMB) to the V2M-P1 Motherboard Express.

Note

ARM recommends that you fit the CoreTile Express A15×2 A7×3 daughterboard

on Motherboard Express site 1, and any optional FPGA daughterboard, for

example the V2F_1XV5, on site 2.

See System interconnect signals on page 2-6.

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ARM AMBA NIC-301 Especificações Página 18