ARM AMBA NIC-301 Especificações descarregar pdf (Página 42)

Hardware Description

ID062813 Non-Confidential

• DDR PLL.

See Test chip SCC Register 11 on page 3-27.

CPU_CLK0_A15 is the default source for A15_CLK.

CPU_CLK2_A7 is the default source for A7_CLK.

You can use the 4-way glitchless multiplexers to select any of the four inputs as the sources for

A15_CLK and A7_CLK. See Test chip SCC Register 11 on page 3-27.

When you write to the SCC registers to change the sources for the MPCore clocks, you can

monitor when the change takes effect by reading the clock status register. See Tes t chip SCC

You can select the polarity of MMB_IDCLK relative to PXLREFCLK. It can be either in

phase with PXLREFCLK or inverted. See Polarities Register bit assignments on page B-17.

You can also use the SCC registers to exercise other options, for example, to select External

Bypass to bypass the PLL and drive the reference clock into the design.

Note

The configuration process bypasses the HDLCD PLL by default.

ARM does not recommend that you select non-default options for the other PLLs and

Figure 2-10 on page 2-26 does not show these options. See Test chip SCC Register 11 on

page 3-27 and Test chip SCC Registers 13, 15, 17, 19, 23, and 25 PLL control registers on

page 3-31.

The MCC and Daughterboard Configuration Controller use the

board.txt

configuration file for

the daughterboard to set the frequency of the daughterboard clock generators and to configure

the SCC registers on power-up or reset. You can also adjust the daughterboard clocks during

run-time by using the motherboard SYS_CFG register interface.

For more information see:

• Power-up configuration and resets on page 2-10.

• Versatile Express

™

Configuration Technical Reference Manual for an example

board.txt

file.

• Motherboard Express µATX Technical Reference Manual.

2.7.2 Daughterboard programmable clock generators

This section describes the daughterboard clock generators and the clocks that the test chip

generates from them to drive the on-chip systems.

The following SCC registers control the PLLs, clock divider blocks and PLL input select

multiplexers:

• Test chip SCC Register 11 on page 3-27

• Test chip SCC Register 12 on page 3-30

• Test chip SCC Registers 13, 15, 17, 19, 23, and 25 PLL control registers on page 3-31

• Test chip SCC Registers 14, 16, 18, 22, 24 and 26 PLL value registers on page 3-33.

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ARM AMBA NIC-301 Especificações Página 42