ARM AMBA NIC-301 Especificações descarregar pdf (Página 159)

HDLCD controller

ID062813 Non-Confidential

Table B-2 shows the bit assignments.

Interrupt Raw Status Register

The INT_RAWSTAT Register characteristics are:

Purpose Shows the unmasked status of the interrupt sources. Writing a 1 to the bit

of an interrupt source forces this bit to be set and generate an interrupt if it

is not masked by the corresponding bit in the Interrupt Mask Register on

page B-7. Writing a 0 to the bit of an interrupt source has no effect.

Use the Interrupt Clear Register on page B-6 to clear interrupts.

Usage constraints There are no usage constraints.

Configurations Available in all HDLCD controller configurations.

Attributes See Table B-1 on page B-3.

Figure B-2 shows the bit assignments.

Figure B-2 Interrupt Raw Status Register bit assignments

Table B-3 shows the bit assignments.

Table B-2 Version Register bit assignments

Bits Name Function

[31:16] PRODUCT_ID Product ID number

0x1CDC

[15:8] VERSION_MAJOR These bits provide the major product version information.

For release r0p0, the value is

0x00

[7:0] VERSION_MINOR These bits provide the minor product version information.

For release r0p0, the value is

0x00

31 43 021

RESERVED

UNDERRUN

VSYNC

BUS_ERROR

DMA_END

Table B-3 Raw Interrupt Register bit assignments

Bits Name Function

[31:4] - Reserved, write as zero, read undefined.

[3] UNDERRUN No data was available to display while DATAEN was active.

This interrupt triggers if the controller does not have pixel data available to drive when DATAEN is active.

When this occurs, the controller drives the default color for the rest of the screen and attempts to display the

next frame correctly.

1 2 ... 154 155 156 157 158 159 160 161 162 163 164 ... 177 178

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ARM AMBA NIC-301 Especificações Página 159