
Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-64
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Figure 3-31 System counter CNTCVL Control Register bit assignments
Table 3-45 shows the bit assignments.
CNTCVU
The CNTCVU Register characteristics are:
Purpose System counter upper 32 bits control register that enables you to read and
write the system counter upper 32 bits.
Usage constraints There are no usage constraints.
Configurations Not applicable.
Attributes See Table 3-43 on page 3-62.
Figure 3-32 shows the bit assignments.
Figure 3-32 System counter CNTCVU Control Register bit assignments
Table 3-46 shows the bit assignments.
CNTFID0
The CNTFID0 Register characteristics are:
Purpose System counter base frequency ID control register that enables you to read
and write the counter frequency.
Usage constraints There are no usage constraints.
31 0
0 00000 0 000000000000 0000 000000 00
0
CNTCVL
Table 3-45 System counter CNTCVL Control Register bit assignments
Bits Name Function
[31:0] CNTCVL Current unencoded value of counter lower 32 bits, CNTCV[31:0]:
Counter disabled Writes to this register pre-load the lower 32 bits of the counter.
Counter enabled The counter ignores writes to this register.
The default is
0x0000_0000
.
31 0
0 00000 0 000000000000 0000 000000 00
0
CNTCVU
Table 3-46 System counter CNTCVU Control Register bit assignments
Bits Name Function
[31:0] CNTCVU Current unencoded value of counter upper 32 bits, CNTCV[63:32]:
Counter disabled Writes to this register pre-load the upper 32 bits of the counter.
Counter enabled The Counter ignores writes to this register.
The default is
0x0000_0000
.
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