ARM AMBA NIC-301 Especificações descarregar pdf (Página 23)

Hardware Description

ID062813 Non-Confidential

Express A15×2 A7×3 daughterboard. See the documentation supplied on the

accompanying media and the Application Notes listing for more information at,

http://infocenter.arm.com

2.3.2 High-Speed Bus (HSB) to other daughterboard

The HSB link to the other daughterboard consists of one bus between the Cortex-A15_A7

MPCore test chip and the daughterboard fitted in the other site on the motherboard. This is a

64-bit multiplexed AXI master bus, HSB M, to the external AXI slave on the other

daughterboard in Site 2.

The HSB connection to the other daughterboard is through:

• The HDRX header on the daughterboard.

• Dedicated headers HDRX1 and HDRX2 on the motherboard.

• Header HDRX on the other daughterboard.

Note

For information about the multiplexing scheme for the AXI buses, see Appendix A Signal

Descriptions.

Note

Application note AN283, Example LogicTile

™

Express 3MG design for a CoreTile

™

Express

A15×2, provides an example AXI design implementing an external multiplexed AXI master bus

at the HDRX header on the FPGA daughterboard in site 2.

2.3.3 Static Memory Bus (SMB)

The SMB connects the Cortex-A15_A7 test chip SMC to the motherboard. You can use it to

access the motherboard peripherals such as:

• NOR flash.

•SRAM.

•Ethernet.

•USB.

• MultiMedia Card (MMC).

• Compact Flash (CF).

• Keyboard and Mouse Interface (KMI).

•CLCD.

• UARTs.

• System registers.

2.3.4 MultiMedia Bus (MMB)

The MMB consists of a video bus that connects the 24-bit RGB HDLCD controller directly to

the motherboard MUXFPGA. The motherboard IOFPGA implements a CLCD controller. The

motherboard MUXFPGA selects the source for the motherboard DVI connector from:

• The MMB from the CoreTile Express A15×2 A7×3. That is, the 24-bit RGB from the

HDLCD controller.

• The MMB from the LogicTile Express daughterboard in site 2.

• The CLCD controller in the motherboard IOFPGA.

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