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Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-15
ID062813 Non-Confidential
3.3.3 Mask operation to define SMC chip select address ranges
The following registers enable you to define SMC Chip Select (CS) base addresses by defining
the 7th and 8th hexadecimal digits of each base addresses:
• Test chip SCC Register 0 on page 3-17
• Test chip SCC Register 1 on page 3-17
• Test chip SCC Register 2 on page 3-18
• Test chip SCC Register 3 on page 3-19.
Each register defines two base addresses, and each base address is defined by 8 match bits and
by 8 mask bits.
0x404
CFGREG42 RW
0x083FFC00
32 A15 configuration register 1.
See Test chip SCC Register 42 on page 3-36.
0x4FC
-
0x408
----Reserved.
Do not write to or read from these registers.
0x500
CFGREG43 RW
0x77700001
32 A7 configuration register 0.
See Test chip SCC Register 43 on page 3-39.
0x504
CFGREG44 RW
0x00008007
32 A7 configuration register 1.
See Test chip SCC Register 44 on page 3-41.
0x5FC
-
0x508
----Reserved.
Do not write to or read from these registers.
0x600
CFGREG45 RW
0x55555500
32 CCI-400 configuration register 0.
See Test chip SCC Register 45 on page 3-42.
0x604
CFGREG46 RW
0x01860038
32 CCI-400 configuration register 1.
See Test chip SCC Register 46 on page 3-44.
0x608
CFGREG47 RW
0x00070000
32 CCI-400 configuration register 2.
See Test chip SCC Register 47 on page 3-45.
0x6FC
-
0x60C
----Reserved.
Do not write to or read from these registers.
0x700
CFGREG48 RW
0x0032F003
32 System information register.
See Test chip SCC Register 48 on page 3-47.
0xFF0
-
0x704
----Reserved.
Do not write to or read from these registers.
0xFF4
APB_CLEAR WO - 32 Write
0x000A50F5
to this register to revert serial control
to the values loaded through the SCC.
See Test chip SCC Register APB_CLEAR on page 3-51.
0xFF8
TC_ID RO
0x00050176
32 Test chip specific device ID register.
See Test chip SCC Register TEST_CHIP_ID on
page 3-52.
0xFFC
CPU_ID RO
0x410FC0F0
32 Cortex-A15_A7 CPU ID register.
See Test chip SCC Register CPU_ID on page 3-52.
Table 3-6 Test chip SCC register summary (continued)
Offset Name Type Test chip reset Width Description
- CoreTile 1
- Express A15×2 A7×3 1
- CoreTile Express A15×2 A7×3 2
- CE Declaration of Conformity 3
- Contents 4
- Appendix B HDLCD controller 5
- Appendix D Revisions 5
- • About this book on page vii 6
- • Feedback on page xi 6
- About this book 7
- Preface 10
- ID062813 Non-Confidential 10
- Feedback 11
- Chapter 1 12
- Introduction 12
- 1.2 Precautions 15
- Chapter 2 16
- Hardware Description 16
- MBM_nRST 29
- Internal resets 32
- 0x0000_0000 38
- 2.7 Clocks 39
- (CLKF + 1) 46
- (CLKOD + 1) (CLKR + 1)x 46
- 2.8 Interrupts 49
- 2.8.2 Interrupts 50
- 2.9 HDLCD 53
- 2.10 DDR2 memory interface 54
- 2.11 Debug 55
- Components Technical 56
- Reference Manual 56
- Chapter 3 58
- UNPREDICTABLE behavior 59
- 3.2 Daughterboard memory map 60
- You can access NOR 0 at 61
- and at 61
- 0x00_0000_0000 62
- 3.3 Test chip SCC registers 69
- SMC_ADDR_MATCH1_0 75
- SMC_ADDR_MASK1_0 75
- DMA_BOOT_ADDR 79
- DAP ROM Default Target ID 82
- DAP ROM Default Instance ID 83
- A15_CRNTCLK[3:0] 88
- A7_CRNTCLK[3:0] 88
- 31 16 15 8 0 92
- Programmers Model 100
- 0x000A50F5 to the 108
- Cortex-A15_A7 CPU ID 110
- 0x2A43_0000 119
- Reserved 120
- 0x2A80_0000 126
- CNTPL0ACR 136
- CNTP_TVAL 139
- CNTVL_CVAL 140
- Appendix A 147
- Signal Descriptions 147
- HDRXHDRY 148
- TRACE (DUAL) TRACE (SINGLE) 148
- Figure A-2 HSB multiplexing 149
- A.3 Header connectors 151
- Appendix B 155
- HDLCD controller 155
- B.1 Introduction 156
- B.2 HDLCD Programmers Model 157
- 31 16 15 8 7 0 158
- FB_BASE_ADDR 163
- FB_LINE_COUNT 164
- RESERVED 164
- FB_LINE_PITCH 165
- 31 12 11 0 167
- Reserved V_SYNC 167
- Reserved V_BACK_PORCH 167
- Reserved V_DATA 168
- Reserved V_FRONT_PORCH 168
- Reserved H_SYNC 169
- Reserved H_BACK_PORCH 169
- Reserved H_DATA 170
- Reserved H_FRONT_PORCH 170
- 31 30 5432 0 173
- BIG_ENDIAN 173
- BYTES_PER_PIXEL 173
- Appendix C 175
- Electrical Specifications 175
- C.1 AC characteristics 176
- Appendix D 177
- Revisions 177
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