ARM Cortex R4F Manual do Utilizador Página 51
- Página / 64
- Índice
- MARCADORES
- ARM CPUs: ARM7, Cortex M3 1
- ARM CPU 2
- Not to scale 3
- ARM Instruction Sets 5
- •ARM Instruction Set 7
- • Thumb Instruction Set 7
- •JazelleInstruction Set 7
- Three Instruction Sets 8
- ARM instruction 10
- Select registers 10
- ARM7 Architecture 11
- ARM CPU Core Organization 12
- ARM7 Features 13
- ARM7 Pipeline Execution 14
- ARM CPU (More) Features 16
- (ARM7TDMI) 17
- ARM7TDMI and ARM9 Pipeline 18
- ARM Architectures 19
- ARM Cortex-M4 20
- ARM Cortex-M3 21
- Data Bus 22
- Address 22
- Result Bus 22
- ARM Cortex-M3 Bus 25
- ARM7: Programming Model 28
- PSR: Program Status Register 30
- SSAT: Saturate Instruction 31
- ARM Procedure Call Standard 32
- Exception vector addresses 33
- The ARM Condition Code Field 35
- 31 28 27 0 35
- Branch Conditions 36
- Bitwise Instructions 38
- Shift Instructions 38
- Interrupt Processing 39
- Exception/Interrupt Handler 40
- Interrupt Stacking 41
- Interrupt Latency 42
- Interrupt Latency Reduction 43
- ARM9 CPU Applications 46
- Sony Playstation 3 (60GB) 47
- ARM 11 (v6) CPU Core 48
- Why ARM 11 (ARMv6) 49
- ARM 11 Applications 50
- Target Applications 51
- ARM11 MPCore 52
- ARMv6 Memory Model 54
- • Run Mode 55
- • Standby Mode 55
- • Shutdown Mode 55
- • Dormant Mode 55
- TMS470 Family MCUs 56
- Electro Mechanical Braking 58
- Micro-Controller 60
- Instrument Cluster 63
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