ARM Cortex R4F Especificações

Application ReportSPNA106– September 2011Initialization of Hercules™ ARM®Cortex™-R4FMicrocontrollersSunil Oak...

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.4 Configure Oscillator MonitorThe HF LPO clock source is used as a reference

www.ti.comStandard Initialization Sequence for Hercules Microcontrollers2.5 Enabling Floating-Point Coprocessor (FPU)The floating-point coprocessor is

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.commov r11, #0x0000mov r12, #0x0000; Switch back to Supervisor Mode (M = 0b10011)

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersWhen the return stack detects a taken return instruction, the PFU issues an in

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.8 Configure Flash AccessThe Flash memory on the Hercules series microcontrol

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersFigure 10. Flash State Machine Write Enable Control Register (FSM_WR_ENA) Addr

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.9 Configure Flash Bank and Pump Power ModesThe Flash banks and pump used on

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersEach of the BANKPWRx fields configures the fall-back mode for a single Flash b

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.comflashWREG->FMAC = 0x00000000; // Select flash bank0flashWREG->FBAC |= 0x

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersflashWREG->FPAC2 = 0x000000FF; // PSLEEP = 255 * 16 HCLK cycles2.10 Clock D

www.ti.com25 VIM Interrupt Address Memory Map ... 2726 FIQ/IRQ Contro

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.comTable 11. GCLK, HCLK , VCLKx Source Register (GHVSRC) Field Descriptions (cont

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersThe asynchronous clock source register (VCLKASRC) is shown in Figure 19.Figure

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.comsystemREG1->CLKCNTL |= 0x00000000U ; // VCLK2 = HCLK/1temp = systemREG1->

www.ti.comStandard Initialization Sequence for Hercules Microcontrollers2.14 Enable Response to ECC Errors in Flash Module and TCRAM ModuleThe flash m

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.18 Run Self-Test on the Flash Module SECDED LogicThe Flash module reads the

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersFigure 23. Memory Self-Test / Initialization Control Register (MSIENA) Address

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.comThe Cortex-R4F CPU can operate in one of several modes:• User mode (USR) is th

Interrupt vector table address space0xFFF820000xFFF820040xFFF82008Phantom VectorChannel 0 VectorChannel 1 VectorChannel 93 VectorChannel 94 Vector0xFF

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.21.1 Example VIM RAM Configurationtypedef void (*t_isrFuncPTR)();#define VIM

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollerserayT0CInterrupt, /* phantomInterrupt for RM4x */spi5HighLevelInterrupt,spi4Lo

3MFlashwithECC64K64K64K64K256KRAMwithECCETM-R4(CPU Trace)Dual Cortex-R4FCPUs in LockstepRTP(RAM Trace)DMAPOMDMMHTU1FTUHTU2EMACSwitched Centrol Resourc

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.21.2 Configure Interrupts to be Fast Interrupts or Normal InterruptsTwo regi

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersThe interrupt enable set register 1 (REQENASET1) is shown in Figure 29.Figure

Referenceswww.ti.comThe VIC port is disabled upon any CPU reset and must be enabled by the application. The VIC is enabledby setting the VE bit in the

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2 Standard Initialization Sequence for Hercules MicrocontrollersA basic sequen

OSCIN/NR/1 to /64INTCLKPLL/NF/1 to /256VCOCLK/OD/1 to /8post_ODCLK/R/1 to /32PLLCLKf = (f / NR) * NF / (OD * R)PLLCLK OSCINf = (f / NR2) * NF2 / (OD2

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.comNOTE: The FMPLL takes (127 + 1024*NR) oscillator cycles to acquire lock to the

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersTable 1. PLL Control Register (PLLCTL1) Field Descriptions (continued)Bit Fiel

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.3 Enable Clock Sources2.3.1 Available Clock Sources on Hercules Microcontrol

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersThe clock source disable register (CSDISSET) is shown in Figure 7.Figure 7. Cl