ARM Cortex R4F Manual do Utilizador descarregar pdf (Página 39)

© G.N. Khan ARM Processors/Cores – EE8205: Embedded Computer Systems Page: 39

Interrupt Processing

Hardware interrupt

request occurs: CPU

finishes , suspends or

abandons the current

instruction and then

initiates an exception

response sequence.

Interrupt Complete:

Interrupted code

continues where it

left off as if nothing

happened.

Exception Response Sequence: CPU

stacks the processor state and return

address, enables Handler Mode,

identifies the requesting device, and

transfers control to the corresponding

Interrupt Service Routine.

Exception Handler / ISR:

1. Preserve R4-R11 as needed.

2. Transfer data between queue

and I/O device.

3. Restore R4-R11 as needed.

4. Return to interrupted code.

Exception Return: Unstack

and restore the processor

state and mode.

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