ARM Cortex R4F Manual do Utilizador descarregar pdf (Página 11)

ARM7 Architecture

• Load/store architecture

• Most instructions are RISCy

Some multi-register operations take multiple cycles

• All instructions can be executed conditionally

ARM7 is a small, low power, 32-bit microprocessor.

Three-stage pipeline, each stage takes one clock cycle

• Instruction fetch from memory

• Instruction decode

• Instruction execution.

 Register read

 A shift applied to one operand and the ALU operation

 Register write

This limits the CPU max clock speed to around 80 MHz on a 0.35-

micron silicon process.

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 63 64

Sem comentários

ARM Cortex R4F Manual do Utilizador Página 11