ARM Cortex R4F Manual do Utilizador descarregar pdf (Página 23)

ARM Cortex-M3

• Implement Thumb-2 instruction subset of ARM Instruction Set.

• Most Thumb-2 instructions are 16-bit wide that are expanded

internally to a full 32-bit ARM instructions.

• ARM CPUs are capable of performing multiple low-level

operations in parallel.

• A hardware sign extender convert 8-16 bit operands to 32-bit

• Load store architecture.

• Barrel shifter allows operand R

to beshited first and then ALU

can perform another operation (e.g. add, subtract, mul etc.)

• Barrel shifter can do 5X = X + 2

X; -7X = X-2

• MAC is memory address calculator for different addressing of

arrays and repetitive address calculations.

• R

-R

GPR, R

-R

special purpose registers i.e. SP, PC and LR

(that holds the return address when a subroutine is called.

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ARM Cortex R4F Manual do Utilizador Página 23