
© G.N. Khan ARM Processors/Cores – EE8205: Embedded Computer Systems Page: 34
Load/Store Instructions
Load/Store Memory Operation Notes
LDR R
,<mem> R
mem
32
[address]
LDRB R
,<mem> R
mem
8
[address] Zero fills
LDRH R
,<mem> R
mem
16
[address] Zero fills
LDRSB R
,<mem> R
mem
8
[address] Sign extends
LDRSH R
,<mem> R
mem
16
[address] Sign extends
LDRD R
t
,R
t2
,<mem> R
t2
.R
t
mem
64
[address]
Addr. Offset must
be imm.
Load/Store Memory Operation Notes
STR R
,<mem> R
mem
32
[address]
STRB R
,<mem> R
mem
8
[address]
STRH R
,<mem> R
mem
16
[address]
STRD R
t
,R
t2
,<mem> R
t2
.R
t
mem
64
[address]
Addr. Offset must
be imm.
These instructions will not affect flags in CPSR!
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