ARM ARM1176JZF-S Manual do Utilizador descarregar pdf (Página 5)

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Data alignment

Prior to architecture v6 data accesses must be appropriately aligned for

access size

Unaligned addresses will produce unexpected/undefined results

Unaligned data can be accessed using multiple aligned accesses

combined with shift/mask operations

Byte access

(byte aligned)

Halfword access

(halfword aligned)

Word access

(word aligned)

3 2 1 0

7 6 5 4

89ab

cdef

101010

Vector Table

Exception Handling

When an exception occurs, the core:

Copies CPSR into SPSR_<mode>

Sets appropriate CPSR bits

Change to ARM state

Change to exception mode

Disable interrupts (if appropriate)

Stores the return address in LR_<mode>

Sets PC to vector address

To return, exception handler needs to:

Restore CPSR from SPSR_<mode>

Restore PC from LR_<mode>

Must be done in ARM state in most cores, but...

...Thumb-2 capable cores can do this in Thumb state

Vector table can also be at

0xFFFF0000 on most cores

FIQ

IRQ

(Reserved)

Data Abort

Prefetch Abort

Software Interrupt

Undefined Instruction

Reset

0x1C

0x18

0x14

0x10

0x0C

0x08

0x04

0x00

1 2 3 4 5 6 7 8 9 10 ... 18 19

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