ARM ARM1176JZF-S Manual do Utilizador descarregar pdf (Página 14)

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Cortex-A8 Integer Pipeline

Instruction Execute / Load Store

Instruction Fetch

F1 F2F0

Instruction Decode

Replay Penalty

D0 D1 D2 D3 D4 E0 E1 E2 E3 E4 E5

Branch Mispredict Penalty

AGU

Queue

RAM

TLB

Branch

Pred.

Early

DEC

Queue

DEC

SEQ

Regfile

Remap

Score

board

& Issue

Logic

Shift SATALU WBBP

Update

Reg

File

Early

DEC

Pending

Replay

Queue

Route MUL2MUL1 WBADD

Shift SATALU WB

Update

AGU Format

Fwd

RAM +

TLB

ALU

MUL

PIPE0

ALU

PIPE1

LOAD

STORE

Update

Optimising code to make use of the processor pipeline is very difficult

Leave it to the compiler!!

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Reference Slides

1 2 ... 9 10 11 12 13 14 15 16 17 18 19

ARM Architecture 1
Overview 1
Programmer’s Model 2
Processor Modes 3
The ARM Register Set 4
Program Status Registers 4
Data alignment 5
Exception Handling 5
Introduction to 6
Instruction Sets 6
Thumb Instruction Set 7
Thumb-2 Instruction Set 7
Processor Cores 8
ARM7TDMI Processor 9
ARM926EJ-S Processor 9
ARM1176JZ(F)-S Processor Core 10
ARM11 MPCore Processor 10
ARM Cortex-M3 Processor 11
ARM Cortex-A8 Processor 11
The Instruction Pipeline 12
Optimal Pipelining 13
Branch Pipeline Example 13
Reference Slides 14
Reference Material 15
Naming Conventions 15
ARMv4T Cores: 16
ARMv5 Cores: 17
ARMv6 Cores: 17
Cortex Cores: 18
TrustZone Computing 18
NEON Media Processor Features 19

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