ARM Cortex-M3 Manual do Utilizador

1ARM Cortex-M3IntroductionARM University Relations

10Cortex-M3 Register SetVery compiler friendlyLoad/Store Architecture32-bit registersFlexible register schemeLinear 32-bit address spaceProcessr8

11Program Status RegisterOne Status Register consisting ofAPSR-Application Program Status Register–ALU flagsIPSR-Interrupt Program Status Register–

12High PerformanceARM processorHigh-bandwidthon-chip RAMHighBandwidthExternalMemoryInterfaceDMABus MasterAPBBridgeKeypadUARTPIOTimerAHBAPBHigh Perform

13Memory MapVery simple linear 4GB memory mapThe Bus Matrix partitions memory access via the AHB and PPB busesDebugSYSTEM AHBThe image cannot be dis

14NXP LPC1311/13/42/43 Block Diagram

15NXP LPC1311/13/42/43 Memory Map

16ARM Cortex-M3Application codeOSSystem Call (SVCall)Undefined InstructionPrivilegedProcessor PrivilegeMemoryInstructions & DataAbortsInterruptsRe

17Memory Protection Unit (MPU)MPU provides access control for various memory regionsZero Latency Memory Protection8 register-stored regionsSame re

18Traditional Method of Atomic Manipulation00000000xxxxx1xx00000100Read byte from SRAMMask and ModifyBit ElementWrite byte to SRAM0x020000000x02000000

19Word aliasPhysical bit32MBBit band alias32MB31MB1MBBit band regionBit band alias32MB31MB1MBBit band regionWrites to a word address in thebit band a

2AgendaCortex-M3 Overviewv7-M Architecture/Programmers ModelData Path and PipelinesTools and mbed Platform

20Conditional ExecutionITTET EQInst 1Inst 2Inst 3Inst 4If–Then (IT) instruction added (16 bit)Up to 3 additional “then” or “else” conditions maybe s

21Interrupt HandlingOne Non-Maskable Interrupt (INTNMI) supported1-240 prioritizable interrupts supportedInterrupts can be maskedImplementation op

22Exception HandlingResetNMIFaultsHard FaultMemory ManageBus FaultUsage FaultSVCallDebug MonitorPendSVSysTick InterruptExternal Interrupt

23Multiple sleep modes supportedControlled by NVICSleep Now–Wait for Interrupt/Event instructionsSleep On Exit–Sleep immediately on return from la

24Single steppingITM (Instrumentation Trace Module)Support for instrumented codeLike “printf” debugging, but single cycle writes to ITM module can

25AgendaCortex-M3 Overviewv7-M Architecture/Programmers ModelData Path and PipelinesTools and mbed Platform

26Cortex-M3 DatapathRegisterBankMul/DivAddressIncrementerALUBAINTADDRI_HADDRAddressRegisterBarrelShifterWritebackALURead DataRegisterWrite DataRegiste

27Cortex-M3 has 3-stage fetch-decode-execute pipelineSimilar to ARM7Cortex-M3 does more in each stage to increase overallperformanceCortex-M3 Pipel

28CycleOperationADDSUBORRANDEORORROptimal PipeliningAll operations here are on registers (single cycle execution)In this example it takes 6 clock cy

29It takes 3 cycles to complete the branchWorst case scenario–indirect branch takenCycleAddressOperation0x8000BX r50x8002SUB0x8FEEORR0x8FECAND0x8FF0

3Microcontrollers are gettingcheap32-bit ARM Cortex-M3 Microcontrollers @ $1Some microcontrollers sell for as little as $0.65Microcontrollers are

30In this example it takes 7 clock cycles to execute 6 instructionsClock cycles per Instruction (CPI) = 1.2The read cycle must complete on the bus

31Store buffer allows STR instruction to finish before storecycle completes on the busBack-to-back STR instructions pipeline on the AHB-Lite bus-Als

32AgendaCortex-M3 Overviewv7-M Architecture/Programmers ModelData Path and PipelinesTools and mbed Platform

33RVMDK Software Development ToolsIncludes ARM macro assembler, compilers (ARM RealView C/C++Compiler, Keil CARM Compiler, or GNU compiler), ARM link

34RVMDK Software Development Tools

35Cortex-M3 Development Platforms

36Rapid Prototyping3D Moulding3D Printing2D/3D DesignWeb FrameworksRapid Prototyping helps industries create new productsControl, communication and

37Getting Started and Rapid Prototyping with ARM MCUsComplete Targeted Hardware, Software and Web 2.0 PlatformmbedLightweight Online CompilerCortex-M3

38mbed Motor Controller Example#include"mbed.h“DigitalOutleftfwd(p16);DigitalOutleftrev(p17);PwmOutpwm(p21);AnalogInpot(p20);intmain(){pwm.period

39DocumentationARM v7-M Architecture Reference Manual (ARM v7-MARM)Cortex-M3 Technical Reference Manual (TRM)ARM Debug Interface V5 Architecture Sp

4ARM Cortex-M3 ProcessorFPBBKPTARMCortex-M3CoreETMInstructionTraceBus MatrixIDDAPJTAG/SWDNVIC1-240 Interrupts8-256 PrioritiesCode Busesto Flashto Code

40University Resourceshttp://www.arm.com/support/university/[email protected]http://www.mbed.org/http://www.keil.com/

41Fin

518 x 32-bit registersExcellent compiler targetReduced pin count requirementsEfficient interrupt handlingPower managementEfficient debug and dev

6ARMv7M ArchitectureNo Cache-No MMUDebug is optimized for microcontroller applicationsVector table contains addresses, not instructionsDIV instru

7ARM and Thumb PerformanceMemory width (zero wait state)05000100001500020000250003000032-bit16-bit16-bit with32-bit stackARMThumbDhrystone 2.1/sec@ 20

8The Thumb-2 instruction setVariable-length instructionsARM instructions are a fixed length of 32 bitsThumb instructions are a fixed length of 16bi

9AgendaCortex-M3 Overviewv7-M Architecture/Programmers ModelData Path and PipelinesTools and mbed Platform