ARM Cortex-M3 Manual do Utilizador descarregar pdf (Página 30)

30



In this example it takes 7 clock cycles to execute 6 instructions



Clock cycles per Instruction (CPI) = 1.2



The read cycle must complete on the bus before the LDR

instruction can complete since there is only one writeback port in

the register file

Cycle

Operation

ADD

SUB

ORR

AND

EOR

LDR

1

2

3

4

5

6

7

8

9

F

D

E

F

D

E

F

E

F

D

E

F

D

Ea

D

F

D

E

F

-

Fetch

D

-

Decode

E

–

Execute

S

-

Stall

Ea

–

LDR address phase

Ed

–

LDR data phase

Ed

S

S

LDR Pipeline Example

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 40 41

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