ARM Cortex-M3 Manual do Utilizador descarregar pdf (Página 21)

21

Interrupt Handling



One Non

-

Maskable Interrupt (INTNMI) supported



1

-

240 prioritizable interrupts supported



Interrupts can be masked



Implementation option selects number of interrupts supported



Nested Vectored Interrupt Controller (NVIC) is tightly coupled with processor core



Interrupt inputs are active HIGH

Cortex

-

M3

Processor Core

INTNMI

NVIC

Cortex

-

M3

1

-

240 Interrupts

INTISR[239:0]

…

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 40 41

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