ARM Cortex-M3 Manual do Utilizador descarregar pdf (Página 6)



ARMv7M Architecture



No Cache

No MMU



Debug is optimized for microcontroller applications



Vector table contains addresses, not instructions



DIV instruction



Interrupts automatically save/restore state



Exceptions programmed in C (No Coprocessor 15

All registers are memory

mapped)



Interrupt controller is part of Cortex

M3 macrocell



Fixed memory map



Bit

banding



Non

Maskable Interrupt (NMI)



Only one processor status reg



Thumb

2 processing core



Mix of 16 and 32 bit instructions for very high code density



Gives complete Thumb compatibility

ARM Cortex

M3 Microcontroller

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ARM Cortex-M3 Manual do Utilizador Página 6