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Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014

Freescale Semiconductor, Inc. 3

Architectural key points

• Internal memories TCM, SRAM, Secure RAM, and GRAM

• External memory controllers for SDRAM, QuadSPIs, FlexBus and SDHC

• DMA, semaphores, security, TrustZone

• Set of peripherals including Ethernet, USB, CAN, SCI, SPI, I

C, audio and display drivers.

For more information, see the Vybrid Reference Manual [2] and the Vybrid Data Sheet [3].

3 Architectural key points

How an application is programmed into the Vybrid SoC has a significant impact on application

performance — specifically, how the application is divided and spread between cores, how peripherals are

set, and which memories and caches are used.

3.1 Clocks

Vybrid controller solutions support several clock domains:

• Cortex-A5 clock; 266, 400–500 MHz

• Platform clock (NIC, Cortex-M4 clock); 133–166 MHz; usual ratio 1:3 to Cortex-A5 clock

• DDR clock; max 400 MHz

• Peripheral; max 83 MHz; usual ratio 1:2 to platform clock.

•Etc.

Find more information in Vybrid Reference Manual [2], chapter “Clock Configuration.”

3.2 NIC-301

The most important part of the architecture is the NIC-301, displayed in the center of Figure 1. The NIC

creates interconnections between masters (cores and DMAs) and slaves (peripherals and memories). All

data transfers go through these interconnections. The NIC architecture determines maximum throughput

between masters and slave, but also adds latency to transfers between them.

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