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Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014

2 Freescale Semiconductor, Inc.

Vybrid architecture

2 Vybrid architecture

Vybrid controller solutions include one Cortex®-A5 core for the rich part of the application and one

Cortex-M4 for the real-time control part of the application, integrated with a large set of peripherals

interconnected by the Network Interconnect (NIC), which is the key point of the architecture.

Figure 1. Vybrid internal architecture

Figure 1 shows the internal architecture of the Vybrid controller solutions. Vybrid controller solutions

integrate the following parts:

• ARM Cortex-A5: Includes FPU single and double precision, NEON Media Processing Engine,

ARM or thumb mode (32 or 16-bit instructions), 1.57 DMIPS per MHz integer performance,

eight-stage single issue pipeline, four-stage load/store pipeline, and five-stage FPU/MPE pipeline,

up to 500 MHz.

• ARM Cortex-M4: Includes single-precision FPU, DSP and SIMD ISA extensions, thumb2 mode

only (16-bit instructions for smaller code size), three-stage pipeline, and 1.25 DMIPS per MHz

performance, up to 166 MHz.

• NIC-301: High-performance optimized AMBA-compliant network infrastructure providing

hardware interconnect matrix between 10 masters and eight slaves. The NIC is optimized for 64-bit

AXI interface. NIC system bus fabric optimized for multi-master data bandwidth.

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