ARM AMBA NIC-301 Manual do Utilizador Página 1

Freescale Semiconductor, Inc.Application Note© 2014 Freescale Semiconductor, Inc. All rights reserved. Vybrid controller solutions are built on new as

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201410 Freescale Semiconductor, Inc.Architectural key pointsto one-way (L2C-310 Techni

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 11Architectural key pointsWe can also use external m

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201412 Freescale Semiconductor, Inc.Architectural key pointsMemory aliases were define

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 13Dual-core solutions6. Random access: penalty if bl

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201414 Freescale Semiconductor, Inc.Dual-core solutionsprogramming, the logical core n

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 15Dual-core solutionsFigure 5. Dual-core startAn exa

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201416 Freescale Semiconductor, Inc.Dual-core solutionsFigure 6. Dual-core startNote t

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 17Latency measurement4.2 Dual-core communication and

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201418 Freescale Semiconductor, Inc.Latency measurementFigure 8. Cortex-M4 latency mea

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 19Latency measurementNote the following:• TCML (CODE

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/20142 Freescale Semiconductor, Inc.Vybrid architecture2 Vybrid architectureVybrid cont

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201420 Freescale Semiconductor, Inc.Latency measurementFigure 9. Cortex-A5 PMCCNTR cod

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 21Latency measurementCortex-A5 optimization in the c

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201422 Freescale Semiconductor, Inc.ConclusionCortex-A5 NOP test results comments:Tabl

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 23References7. [7] Vybrid Security reference manual

Document Number: AN4947Rev. 007/2014Information in this document is provided solely to enable system and software implementers to use Freescale produc

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 3Architectural key points• Internal memories TCM, SR

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/20144 Freescale Semiconductor, Inc.Architectural key points3.2.1 Sharing NIC nodesFigu

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 5Architectural key pointsis interrupted and M4 is co

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/20146 Freescale Semiconductor, Inc.Architectural key points3.4 NIC transfer latencyThe

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 7Architectural key pointsLatencies for read/write ar

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/20148 Freescale Semiconductor, Inc.Architectural key points3.6 Bus width and the trans

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 9Architectural key pointsCA5 caches:• Two-way set-as