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Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014

12 Freescale Semiconductor, Inc.

Architectural key points

Memory aliases were defined to cancel additional latency in the Cortex-M4 core — see Table 4. As a

result, Cortex-M4 thinks that it is accessing memory under 0x2000_0000, so it is not adding one clock

cycle, but it physically accesses memory above 0x2000_0000, to where the alias points.

3.11.3 SRAM memory throughput and latencies

The on-chip SRAM (OCRAM) itself does not have any latency once it is addressed to serve data.

Similarly, random access does not add any additional penalty or latency. The only latency is on the NIC

which will include read/write issue, read/write accept and the buffering:

1. Initial number clocks on the NIC. Minimum three for read and five for write.

2. Burst available. The NIC burst request required (invoked by cache or DMA), every clock 64-bit =

8B of data.

3.11.4 SDRAM throughput and latencies

Vybrid integrates a SDRAM controller that works on platform frequency (133-166 MHz). SDRAM is

connected to the controller using 16-bit or 8-bit bus width. Maximum frequency is 400 MHz. The SDRAM

controller can be synchronized to platform frequency only in ratio 2:1, which is not possible on Vybrid.

This creates an additional penalty of five platform clocks to synchronize different clock domains prior to

each transfer (worse latency, better throughput).

SDRAM controller supports burst mode — for each SDRAM clock, 4B are transferred (DDR per 16-bit

bus width on 400 MHz). Data are stored in internal read and write buffers. The SDRAM memory controller

is connected to the NIC via 64-bit bus width. Each transfer to the NIC in the case of burst can transfer 8B

per platform clock (64-bit AXI bus on 133-166 MHz). However, 32B of data can be transferred in four

platform clock cycles + initial clock cycles number.

Initial clock number depends on type of the SDRAM memory LP-DDR2/ DDR3 and the type of NIC

buffering:

1. NIC master request (two-four platform clocks)

2. NIC slave accept (eight platform clocks - clock domain synchronization takes five platform

clocks)

3. Buffering two-four platform clocks

4. Get the first byte from the SDRAM memory (seven SDRAM clocks, depends on the memory)

5. Access within page hit 6-1-1-1 SDRAM clocks

0x1800_0000-0x1EFF_FFFF 112 0x3000_0000 Reserved CM4 FlexBus code alias

0x1F00_0000-0x1F7F_FFFF 8 0x3f00_0000 Reserved CM4 OCRAM code alias

0x1F80_0000-0xFFF_FFFF 8 N/A 0x1f80_0000-0x1FFF_FFFF CM4 TCML (code)

Table 4. Vybrid memory aliases for Cortex-M4 (continued)

CM4 Address Range

[Start Addr – End Addr]

Size (MB) CM4 Alias

System Address (A5)

[Start Addr – End Addr]

Region Description

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 23 24

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