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Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014

Freescale Semiconductor, Inc. 11

Architectural key points

We can also use external memories with integrated memory controllers for SDRAM (LPDDR2 and

DDR3), QuadSPIs, FlexBus, NAND and SDHC.

3.11.1 Cortex-M4 tightly coupled memory (TCM)

The TCM is standard SRAM memory which is connected directly to Cortex-M4 via local memory

controller (see Figure 4). It is divided into two parts: the lower half connected on code bus and the upper

half connected on system bus. Therefore, Cortex-M4 can access TCM within one clock cycle — without

additional latency. Accordingly, it is recommended to use TCM for code/data that need to be accessed

frequently and/or with minimal and stable latency. The best example is ISR code and process data

variables. TCM can be accessed by Cortex-A5 core using the back door. This access is slower because it

has to go through NIC and port splitter (see Figure 1). The back door is intended to load the code and data

into TCM by Cortex-A5 (primary core) prior to running Cortex-M4 (secondary core). Using TCM by

Cortex-M4 core allows true real-time performance of the application to be achieved.

Figure 4. TCM and cache connected to Cortex-M4

3.11.2 Cortex-M4 memory aliases

Cortex-M4 uses modified Harvard architecture with code and system buses, where the address defines

which bus is used. Instruction and vector fetches on the system bus (addr >= 0x2000_0000) are registered

internally with an additional cycle of latency.

Table 4. Vybrid memory aliases for Cortex-M4

CM4 Address Range

[Start Addr – End Addr]

Size (MB) CM4 Alias

System Address (A5)

[Start Addr – End Addr]

Region Description

0x0000_0000-0x007F_FFFF 8 0x0000_0000 0x0000_0000-0x007F_FFFF Boot ROM

0x0080_0000-0x0FFF_FFF 248 0x8080_0000 Reserved CM4 DDR code alias

0x1000_0000-0x17FF_FFFF 128 0x2000_0000 Reserved CM4 QuadSPI0 code alias

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 23 24

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