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Trace Port Interface Unit
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 11-10
ID072410 Non-Confidential
Table 11-7 shows the ITATBCTR2 bit assignments.
11.3.7 Integration ITM Data
The Integration ITM Data characteristics are:
Purpose Trace data integration testing.
Usage constraints You must set bit [1] of TPIU_ITCTRL to use this register. See Integration
Mode Control, TPIU_ITCTRL on page 11-11.
Configurations This register is available in all processor configurations.
Attributes See Table 11-1 on page 11-5.
Figure 11-8 shows the Integration ITM Data bit assignments.
Figure 11-8 Integration ITM Data bit assignments
Table 11-8 shows the Integration ITM Data bit assignments.
Table 11-7 ITATBCTR2 bit assignments
Bits Name Function
[31:1] - Reserved
[0] ATREADY1, ATREADY2 This bit sets the value of both the ETM and ITM ATREADY
outputs, if the TPIU is in integration test mode.
31 30 29 28 27 26 25 24 23 16 15 8 7 0
ITM data 2 ITM data 1 ITM data 0
ETM byte count
ETM ATVALID input
ITM byte count
ITM ATVALID input
Reserved
Table 11-8 Integration ITM Data bit assignments
Bits Name Function
[31:30] - Reserved
[29]
ITM ATVALID input Returns the value of the ITM ATVALID signal.
[28:27]
ITM byte count Number of bytes of ITM trace data since last read of Integration ITM Data Register.
[26]
ETM ATVALID input Returns the value of the ETM ATVALID signal.
[25:24]
ETM byte count Number of bytes of ETM trace data since last read of Integration ETM Data Register.
[23:16]
ITM data 2
ITM trace data. The TPIU discards this data when the register is read.
[15:8]
ITM data 1
[7:0]
ITM data 0
- Technical Reference Manual 1
- Cortex-M3 2
- Contents 3
- List of Tables 5
- List of Figures 7
- • About this book on page x 9
- • Feedback on page xiii 9
- About this book 10
- Preface 11
- Other publications 12
- Feedback 13
- Chapter 1 14
- Introduction 14
- 1.1 About the processor 15
- 1.2 Features 16
- 1.3 Interfaces 17
- 1.4 Configurable options 18
- 1.5 Product documentation 19
- 1.6 Product revisions 22
- 0xE000ED14 23
- Chapter 2 25
- Functional Description 25
- 2.1 About the functions 26
- 2.2 Interfaces 28
- Chapter 3 31
- Programmers Model 31
- 3.3 Instruction set summary 34
- — STKALIGN bit to 1 40
- — UNALIGN_TRP bit to 1 40
- 3.4 System address map 41
- LDRH, STR, STRH 42
- 3.5 Write buffer 44
- 3.6 Exclusive monitor 45
- 3.7 Bit-banding 46
- Figure 3-2 Bit-band mapping 47
- 3.9 Exceptions 50
- Chapter 4 52
- System Control 52
- 4.1 About system control 53
- 4.2 Register summary 54
- 4.3 Register descriptions 56
- Chapter 5 58
- Memory Protection Unit 58
- 5.1 About the MPU 59
- 5.3 MPU programmers model 61
- Chapter 6 62
- 6.1 About the NVIC 63
- 6.3 NVIC programmers model 65
- Chapter 7 67
- 7.1 About debug 68
- 0xE000ED00 69
- 0xE00FF000 70
- 7.2 About the AHB-AP 72
- 7.3.2 FPB programmers model 76
- Chapter 8 77
- 8.1 About the DWT 78
- 8.3 DWT Programmers Model 80
- 0x40000000 81
- 0x4F000000 81
- 0x10000000 81
- 0x1F000000 81
- Chapter 9 82
- 9.1 About the ITM 83
- 9.3 ITM programmers model 85
- PRIVMASK 86
- Chapter 10 87
- 10.1 About the ETM 88
- Figure 10-1 ETM block diagram 89
- 10.2.9 Operation 94
- 10.3 ETM Programmers model 95
- Embedded Trace Macrocell 100
- ID072410 Non-Confidential 100
- Reserved 102
- 26 25 24 102
- Trace control enable 102
- Reserved, RAZ 106
- ETM powered up 106
- TRIGGER output value 107
- Chapter 11 109
- Trace Port Interface Unit 109
- 11.1 About the Cortex-M3 TPIU 110
- 11.3 TPIU programmers model 113
- TRIGGER input value 116
- Appendix A 122
- Revisions 122
- Glossary 129
- 0x00000000 132
- 0x1FFFFFFFF 132
- 0xE0040000 133
- 0xE00FFFFF 133
- 0x1FFFFFFF 133
- 0xE0000000 134
- 0xE003FFFF 134
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