manuais ARM Cortex r1p3

Arm Cortex r1p3 Ficha Técnica (138 páginas)

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Reference manual

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Contents

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List of tables

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List of figures

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1 Referenced document

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2 System and memory overview

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2.2 Memory organization

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2.3 Embedded SRAM

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2.4 Flash memory overview

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2.5 Physical remap

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Interrupts RM0352

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Table 3. Interrupt vectors

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(continued)

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5.1 Introduction

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5.2 Clock generation

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Figure 2. Clock generation

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5.3 Reset generation

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5.3.2 Power-on reset

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5.3.3 ECC reset

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5.3.4 Watchdog reset

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5.3.5 System reset request

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5.3.6 Lockup reset

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5.3.7 Recall done

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6.3.4 Command register

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MASS ERASE

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0-Unlocked

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1NoLocked

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1 Yes Unlocked

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Watchdog timer (WDG) RM0352

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Table 26. WDG register list

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dual timer module (SP804)

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8.2 Functional overview

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8.2.2 Functional description

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Free running counter blocks

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Interface reset

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Prescaler operation

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Timer operation

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Interrupt behavior

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8.3 Programmer's model

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8.3.2 Register descriptions

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Load register, TimerXLoad

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".

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9.4 Configuring SysTick

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C bus interface RM0352

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Table 70. I

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C register list

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10.2.5 I

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C status register (I2C_SR)

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11.1 Features

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11.2 Clock prescaler

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11.5.4 SSPRTINTR

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11.5.1 SSPRXINTR

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11.5.2 SSPTXINTR

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11.5.3 SSPRORINTR

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12.1 Features

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12.2 IrDA SIR block

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12.3 Baud rate generator

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12.4 Interrupts

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12.4.1 UARTMSINTR

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12.4.2 UARTRXINTR

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12.4.3 UARTTXINTR

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12.5 UART registers

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12.6 Register descriptions

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