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Cortex-M3 / Cortex-M3 with ETM (AT420/AT425)

Date of Issue: 12-Nov-2008 ARM Errata Notice Document Revision 2.0

PR326-PRDC-009450 v2.0

Non Confidential

532314: DWT CPI counter increments during sleep

Status

Affects: product Cortex-M3, Cortex-M3 with ETM.

Fault status: Cat 3, Present in: r0p0,r1p0,r1p1,r1p1-00rel0,r1p1-01rel0, Fixed in r2p0-00rel0.

Description

The DWT contains a number of counters for the profiling of applications. The CPI counter is used to indicate the

total number of clock cycles beyond the first cycle of each instruction. The counter is specified to not increment

whilst the core is sleeping but for previous revisions it does increment. This results in sleep cycles being

counted as program execution cycles.

Conditions

1. The CPI counter in the DWT is enabled

2. Core sleeps during profiling

Implications

Profiling information could be calculated incorrectly if the following calculation is used:

InstructionCount = CycleCount – (CPIcount+LSUcount+INTcount+SLEEPcount) + FOLDcount

Workaround

The number of sleep cycles given by SLEEPCNT can be subtracted from the CPI cycle count to obtain the

correct CPI cycle information. Use the following equation:

InstructionCount = CycleCount – (CPIcount+LSUcount+INTcount) + FOLDcount

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