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Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-20
ID013010 Non-Confidential, Unrestricted Access
14.12 Load and Store Double instructions
This section describes the cycle timing behavior for the
LDRD
and
STRD
instructions.
The
LDRD
and
STRD
instructions:
• Are normally single-cycle issue. Both the base and any offset register are Very Early Regs.
• Are 3-cycle issue if offset or pre-increment addressing with a negative register offset is
used. Both the base and any offset register are Very Early Regs.
• Take only one memory cycle if the address is doubleword aligned.
• Take two memory cycles if the address is not doubleword aligned.
Table 14-15 shows the cycle timing behavior for
LDRD
and
STRD
instructions.
Table 14-16 shows the explanation of
<addr_md_1cycle>
and
<addr_md_3cycle>
used in
Table 14-15.
Table 14-15 Load and Store Double instructions cycle timing behavior
Example instruction Cycles
Cycles with
base writeback
Memory
cycles
Result
latency
(LDRD)
Result latency
(base register)
Address is doubleword aligned
LDRD R0, R1, <addr_md_1cycle>
a
12 1 2, 22
LDRD R0, R1, <addr_md_3cycle>
a
34 1 4, 44
Address not doubleword aligned
LDRD R0, R1, <addr_md_1cycle>
a
22 2 2, 32
LDRD R0, R1, <addr_md_3cycle>
a
44 2 4, 54
a. See Table 14-16 for an explanation of
<addr_md_1cycle>
and
<addr_md_3cycle>
.
Table 14-16 <addr_md_1cycle> and <addr_md_3cycle> LDRD example instruction explanation
Example instruction Very Early Reg Comments
<addr_md_1cycle>
LDRD <Rt>, <Rt2>, [<Rn>, #<imm>] (!) <Rn>
If post-increment addressing, pre-increment
addressing with an immediate offset or a positive
register offset, then 1-issue cycle
LDRD <Rt>, <Rt2>, [<Rn>, <Rm>] (!) <Rn>, <Rm>
LDRD <Rt>, <Rt2>, [<Rn>], #<imm> <Rn>
LDRD <Rt>, <Rt2>, [<Rn>], +/-<Rm> <Rn>, <Rm>
<addr_md_3cycle>
LDRD <Rt>, <Rt2>, [<Rn>, -<Rm>] (!) <Rn>,<Rm>
If pre-increment addressing with a negative
register offset, then 3-issue cycles
- -R4 and Cortex-R4F 1
- Cortex-R4 and Cortex-R4F 2
- Contents 3
- Chapter 15 AC Characteristics 5
- Appendix B ECC Schemes 6
- Appendix C Revisions 6
- List of Tables 10
- List of Figures 13
- • Feedback on page xxi 16
- About this book 17
- Preface 18
- Feedback 21
- Chapter 1 22
- Introduction 22
- 1.1 About the processor 23
- 1.2 About the architecture 24
- AXI master bus 25
- AXI slave bus 25
- 1.5 Power management 33
- 1.6 Configurable options 34
- 0xFFFF0000 36
- 1.7 Execution pipeline stages 38
- 1.8 Redundant core comparison 40
- 1.9 Test features 41
- Chapter 2 47
- Programmer’s Model 47
- 2.2 Instruction set states 49
- 2.3 Operating modes 50
- 2.4 Data types 51
- 2.5 Memory formats 52
- 2.6 Registers 53
- Program status registers 55
- 2.7 Program status registers 56
- 2.8 Exceptions 62
- LDM ..,{..pc}^ 63
- SUBS PC, R14_irq, #4 64
- SUBS PC, R14_fiq, #4 65
- Register on page 4-35 67
- Imprecise abort masking 69
- Memory barriers 69
- Chapter 3 76
- 3.1 Initialization 77
- 3.2 Resets 81
- 3.3 Reset modes 82
- 3.4 Clocking 84
- Chapter 4 85
- VariantImplementor 98
- 31 23 20 19 16 15 4 3 0 98
- 29 28 19 18 16 15 3 2 0 100
- SReserved 101
- 31 16 8 7 1 0 101
- ReservedDRegion 101
- System Control Coprocessor 102
- Security extension 103
- ARMv4 Programmer’s model 103
- 31 12 11 8 7 4 3 0 103
- Reserved 103
- 0x00000000 105
- Reserved FCSE TCM PMSA VMSA 106
- Auxiliary Control Register 106
- Cache coherence 106
- Outer shareable 106
- Exclusive instructions 115
- Barrier instructions 115
- SMC instructions 115
- Reserved Level 119
- IRQ = 0x18 120
- 0x0000001C 121
- 0xFFFF0000-0xFFFF001C 121
- Bits Field Function 134
- [4:0] Reserved SBZ 134
- Reserved Region 137
- Figure 4-38 Cache operations 139
- Base address 142
- 31 12 11 7 6 2 1 0 142
- Reserved Size 142
- Privilege access 144
- AXI slave enable 144
- 31 16 15 78430 153
- [11:0] Reserved SBZ 156
- Chapter 5 160
- Prefetch Unit 160
- 5.1 About the prefetch unit 161
- 5.2 Branch prediction 162
- 5.3 Return stack 164
- Chapter 6 165
- 6.1 About the events 166
- 6.2 About the PMU 170
- 6.4 Event bus interface 183
- Chapter 7 184
- Memory Protection Unit 184
- 7.1 About the MPU 185
- Region 1 188
- Region 2 188
- Guard region 189
- 7.2 Memory types 190
- 7.3 Region attributes 192
- 7.5 MPU faults 195
- Chapter 8 197
- Level One Memory System 197
- 8.3 Fault handling 203
- 8.4 About the TCMs 209
- 8.5 About the caches 214
- Clean data cache by set/way 221
- 8.8 Error detection events 232
- Chapter 9 234
- Level Two Interface 234
- 9.1 About the L2 interface 235
- 9.2 AXI master interface 236
- LDMIA R10, {R0-R5} 250
- R10 = 0x1010 250
- 9.4 AXI slave interface 253
- 0x10000000 265
- Chapter 10 266
- Power Control 266
- 10.1 About power control 267
- 10.2 Power management 268
- Chapter 11 270
- 11.1 Debug systems 271
- 11.2 About the debug unit 272
- 11.3 Debug register interface 274
- DSAR CP14 c0, Debug Self 279
- Valid bits 281
- 31 12 11 2 1 0 281
- Bits Reset value Description 292
- Breakpoint value 292
- 0x00000007 293
- 0x0000000F 293
- 0x0000001F 293
- 0x7FFFFFFF 293
- 0xFFFFFFFC 294
- Lock implemented bit 298
- 11.5 Management registers 301
- Claim tag set 302
- 0xC5ACCE55 303
- Register number Function 305
- 11.6 Debug events 308
- 11.7 Debug exception 310
- — + 8 for ARM state 311
- 11.8 Debug state 313
- 11.9 Cache debug 319
- Example 11-15 Reading the PC 333
- Reading memory 334
- Chapter 12 342
- FPU Programmer’s Model 342
- Figure 12-1 FPU register bank 344
- 12.3 System registers 345
- Implementer Part number 346
- 31 24 23 22 16 15 8 7 4 3 0 346
- SVRM TE SPSR D DP 349
- Reserved I DNSP LS 350
- 12.4 Modes of operation 351
- 0xFF 0x7FF 352
- FCMPE(Z) 353
- Chapter 13 355
- Integration Test Registers 355
- Register (ITCTRL) 358
- Chapter 14 365
- • Dual issue on page 14-34 366
- Thumb instructions 369
- <Rn> 373
- 14.5 Media data-processing 374
- 14.7 Multiplies 376
- 14.8 Divide 378
- 14.9 Branches 379
- <addr_md_1cycle> 381
- <addr_md_3cycle> 381
- LDR R5, [R2, #4]! 382
- LDR R6, [R2, #0X10]! 383
- LDR R7, [R2, #0X20]! 383
- <addr_md_3cycle> 384
- RFEIA <Rn> 388
- SRSIA #<mode> 388
- MCR <cond> 390
- MRC <cond> 390
- 1- - - 392
- 14.23 Dual issue 398
- Chapter 15 401
- AC Characteristics 401
- 15.1 Processor timing 402
- Appendix A 414
- Processor Signal Descriptions 414
- A.2 Global signals 416
- A.3 Configuration signals 417
- A.5 L2 interface signals 421
- A.6 TCM interface signals 426
- A.8 Debug interface signals 430
- A.9 ETM interface signals 432
- A.10 Test signals 433
- A.11 MBIST signals 434
- A.12 Validation signals 435
- A.13 FPU signals 436
- Appendix B 437
- ECC Schemes 437
- Appendix C 439
- Revisions 439
- Glossary 442
- Write response channel (B) 444
- WT See Write-through 456
- Cache terminology diagram 456
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