Arm Cortex R4F Manual do Utilizador descarregar pdf (Página 263)

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101

Level Two Interface

ID013010 Non-Confidential, Unrestricted Access

Note

For tag RAM writes, only bits [23:0] of the data bus are used. If two tag RAMs are written at

the same time, they are both written with the same data. To write only one tag RAM using the

AXI Slave, select only one RAM with bits [18:15] of the address bus.

[31:30] Not used, read-as-zero

[29:23] ECC, way 0/1

[22] Valid, way 0/1

[21:0] Tag value, way 0/1

Table 9-39 Tag register format for writes, no parity or ECC

Data bit Description

[63:23] Not used, read-as-zero

[22] Valid, all ways

[21:0] Tag value, all ways

Table 9-40 Tag register format for writes, with parity

Data bit Description

[63:24] Not used, read-as-zero

[23] Parity. all ways

[22] Valid, all ways

[21:0] Tag value, all ways

Table 9-41 Tag register format for writes, with ECC

Data bit Description

[63:30] Not used, read-as-zero

[29:23] ECC, all ways

[22] Valid, all ways

[21:0] Tag value, all ways

Table 9-38 Tag register format for reads, with ECC (continued)

Data bit Description

1 2 ... 258 259 260 261 262 263 264 265 266 267 268 ... 455 456

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